Question 705044

SCQMEDIUM

The logic levels $H$ and $L$ at different locations in a digital circuit are found to be as shown in the figure. Based on these observations, which of the logic gates is not behaving as an ideal NAND gate?

(A)

$G_2$

(B)

$G_3$

(C)

$G_4$

(D)

$G_1$

Detailed Solution

A NAND gate outputs $L$ only when both inputs are $H$ . Looking at $G_4$ , the inputs are $L$ and $H$ . The output is given as $L$ . An ideal NAND gate with inputs $(L, H)$ should yield $H$ (since $0 \cdot 1 = 0$ , NOT $0 = 1$ ). Since the output is $L$ , $G_4$ is not behaving as an ideal NAND gate.

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