Question 705044
SCQMEDIUM
The logic levels and at different locations in a digital circuit are found to be as shown in the figure. Based on these observations, which of the logic gates is not behaving as an ideal NAND gate?
(A)
(B)
(C)
(D)
Detailed Solution
A NAND gate outputs only when both inputs are . Looking at , the inputs are and . The output is given as . An ideal NAND gate with inputs should yield (since , NOT ). Since the output is , is not behaving as an ideal NAND gate.
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